In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETS), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs (Field-Effect Transistors) incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of nanometers in width. Modern FinFET integrated circuits are formed on the surfaces of semiconductor substrates, which are mostly silicon substrates. Individual transistors of the FinFET integrated circuit are electrically isolated from each other by isolation structures formed on the surface of the respective semiconductor substrates. The electrical isolation structures include, for example, shallow trench isolation (STI) regions.
In general, conventional methods of producing an STI feature include first forming a hard mask over the semiconductor substrate, for example, silicon. A trench etching pattern is photolithographically formed over a hard mask dielectric layer, followed by etching through the dielectric hard mask and thereafter etching a trench in the semiconducting substrate surrounding active regions to form an STI feature. Subsequently, the photoresist etching mask is removed and the STI feature is back-filled with a dielectric insulating material. The hard mask layer may also be patterned using a self-aligned double patterning (SADP) scheme.
Conventionally, STI regions are etched with a sequential process flow, where the hard mask layers are etched, followed by etching of the silicon trench. Etching is frequently performed by a plasma enhanced etching process, for example reactive ion etching (RIE). Typically, in a plasma etching process an etchant source gas supplied to an etching chamber where the plasma is ignited to generate ions from the etchant source gas. Ions are then accelerated towards the process wafer substrate, frequently by a voltage bias, where they remove silicon material (etch) from the process wafer. Various gas chemistries are used to provide variable etching rates for different etching target materials. Frequently used etchant sources include chlorine and bromine based etchants, for example Cl2 and HBr. As device sizes continue to decrease, however, it becomes more difficult to control the rate at which the silicon material is etched from the process wafer. As such, an undesirable variability may be introduced into the process with trenches of varying depths produced due to uneven etching.
Further, STI regions are conventionally back-filled using one of the two methods: high-density plasma chemical vapor deposition (HDP) and high aspect-ratio process (HARP) for the gap-filling. The HDP may be used to fill gaps with aspect ratios less than about 6.0 without causing voids. The HARP may be used to fill gaps with aspect ratios less than about 7.0 without causing voids. As device sizes continue to decrease, however, the gap fill of STI openings becomes problematic, and the process window for successful gap filling is narrowed. For example, voids may be formed because deposition at the opening of the STI trenches reduces deposition towards the bottom of the trenches. Such voids may cause faulty devices and contribute to yield loss.
Accordingly, it is desirable to provide semiconductor devices and related fabrication methods that provide electrical isolation but without the need to etch trenches into the silicon process wafer. In addition, it is desirable to provide semiconductor devices and related fabrication methods that provide electrical isolation but without the need to gap-fill the etched trenches. Furthermore, other desirable features and characteristic of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.